# Edge Blue (edge.blue) — Machine-Readable Architecture Specification

> Sovereign Attested Edge Infrastructure fusing 45-50 TOPS NPU Silicon, Hardware Enclaves (Intel TDX / AMD SEV-SNP), Memory Bus Encryption, and HTTP 402 Machine Settlement.

## System Overview
- **Platform**: Edge Blue (`edge.blue`)
- **Operator**: Corrente Labs, Inc. (Delaware C-Corporation)
- **Architecture**: Distributed Confidential Hardware Enclaves with Local NPU Tensor Acceleration
- **Clearinghouse Protocol**: HTTP 402 Machine Settlement & IETF SCITT Hardware Receipts

## Silicon & Hardware Registers
- **NPU Acceleration**: 45–50 TOPS dedicated on-die tensor execution (Intel Core Ultra, AMD Ryzen AI, Qualcomm Snapdragon X Elite).
- **Execution Enclaves**: Intel TDX (Trust Domain Extensions), AMD SEV-SNP (Secure Encrypted Virtualization), ARM CCA.
- **Hardware Register Mapping**:
  - `RTMR0`: Cryptographic hash of virtual BIOS / TDVF bootloader.
  - `RTMR1`: Cryptographic hash of isolated guest kernel and initrd.
  - `RTMR2`: Cryptographic hash of OS runtime configuration and drivers.
  - `RTMR3`: Cryptographic hash of loaded AI model weights, neural code, and runtime state measurements.
- **Memory Bus Protection**: Hardware AES-128/256 memory encryption (MKTME) protecting DDR5, LPDDR5X, and CXL memory interconnects.

## Economic Rails (HTTP 402)
- **Protocol**: HTTP 402 Payment Required machine-to-machine micropayments.
- **Inference Latency**: Sub-5ms on local silicon.
- **Receipt Schema**: `vaara.receipt/v1` and `x402.compute-session/v0` binding model execution to signed CPU fuse quotes.
- **Settlement Rails**: Multi-rail settlement via Ashlar Blue (`ashlar.blue`).